The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS) technology.
The convergence of various high speed data communication technologies (e.g., Ethernet, fiber channel, IEEE firewire links) into the gigabit domain has focused the efforts of integrated circuit designers on developing high speed circuit techniques for processing broadband signals. Similarly, efforts directed at developing low cost and low power dissipation circuits have been driven by the explosive growth in wireless media for voice and data communications.
A circuit block that is commonly found in voice and data communication applications is a phase-locked loop (PLL). The primary function of the PLL is to maintain a fixed phase relationship between an input (e.g., clock) signal and a reference signal. A PLL designed for a digital application typically includes a phase and/or frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), and an (optional) divider. The phase detector determines the phase differences between an input signal (i.e., an input data stream or an input clock) and a reference signal derived from the VCO, and generates a detector output signal indicative of the detected phase differences. The charge pump receives the detector output signal and generates a set of phase error signals (e.g., UP and DOWN currents fed into the filter). The loop filter filters the phase error signals to generate a control signal that is then used to adjust the frequency of the VCO such that the phases of the two signals provided to the phase detector are locked. When the phases of the two signals are locked, the respective frequencies of the two signals are exactly the same.
FIG. 1 is a simplified block diagram of a conventional phase locked loop 10. An input signal is provided to a phase detector 12 that also receives a reference signal from a divider 20. The input signal can be a clock signal, a data stream, or some other types of signal having phase and/or frequency information to which the phase locked loop can be locked. The reference signal is typically a clock signal used to trigger the phase detector 12. Phase detector 12 generates an output signal indicative of the timing differences (i.e., the phase differences) between the input signal and the reference signal. The output signal from the phase detector 12 is provided to a charge pump 14 that generates an output signal indicative of the detected phase error between the input and reference signals. In some designs, the charge pump output signal is logic high if the phase of the input signal is early (or late) relative to that of the reference signal, logic low if the phase of the input signal is late (or early) relative to that of the reference signal, and tri-stated for a period of time between clock edges.
The charge pump output signal is provided to a loop filter 16 that filters the signal with a particular transfer characteristic to generate a control signal. The control signal is then provided to, and used to control the frequency of, a voltage-controlled oscillator (VCO) 18. VCO 18 generates an output clock having a frequency can be adjusted by the control signal at the input of VCO. The output clock is provided to divider 20 that divides the frequency of the output clock by a factor of N to generate the reference signal. Divider 20 is optional and not used when the frequency of the output clock is the same as that of the input signal (i.e., N=1). The control signal adjusts the frequency of VCO 18 such that the frequencies of the two signals provided to phase detector 12 are locked when the phase locked loop 10 is locked.
In typical PLLs, signals are transmitted between components in a non-differential manner. Signals transmitted in this manner, however, are subject to a number of shortcomings. For example, noise from power supply fluctuations and substrate can relatively easily affect the quality of such signals causing jitters and other problems. Hence, it would be desirable to implement the PLL in a fully differential architecture that would significantly reduce jitter and improve overall noise performance.
Furthermore, modern day devices and applications continually demand improved performance criteria including high speed, low power dissipation, and low cost, from their constituent components. To realize and meet such performance criteria, it would be desirable to implement the PLL in low-cost CMOS technology that allows for increased levels of integration.